The Quantum Architecture Research Center investigates system architectures for realistic, programmable, arbitrary-scale quantum computers. Our focus is on components and systems that provide low-overhead fault-tolerance to enable solid-state quantum computation and application of quantum information to real-world problems. We are interested in any promising technology for large-scale quantum computation.

A practical implementation of Shor's algorithm on 1024-bit numbers can require 10⁸ qubits and greater than 10¹² operations. Consequently, methods for investigating these algorithms must be able to account for the dynamics of large collections of qubits. Since errors arise during communication, qubit operations, data storage, and measurement, any methodology for investigating quantum algorithms must properly account for these sources of errors. Here, greater realism leads to greater fidelity of results.

Taking our inspiration from large-scale VLSI design, we treat quantum algorithms as circuits to be optimized, partitioned, and simulated. We have developed optimizations to improve communication accuracy (through teleportation), error correction efficiency (via selective removal of operations), and communication locality (via locality-aware partitioning). We have also investigated techniques for accellerating the process of evaluating the error properties of quantum circuit layouts.

We are interested in developing optimal hardware organizations for expressing quantum circuits, such as Qalypso, at the right. Qalypso provides customized ancilla generation for each local computation or memory storage region. It also provides custom EPR generation and teleportation resources to optimize communication behavior. Needless to say, the Qalypso archictecture is a compilation target for a quantum computer aided design (QCAD) flow. We describe one such tool, called “Quadence” in the next section.

One particularly fruitful technique for investigating quantum computing at “scale,” is to utilize quantum computer aided design (QCAD) tools. The basic philosophy behind QCAD tools is to produce as realistic an implementation of an input quantum circuit as possible in a given technology. The output of QCAD tools can include a full layout, control program (“schedule”), and analysis of the error behavior of the circuit.

At the left is Quadence, a QCAD tool for Ion Trap Quantum Computers. Quadence takes an input quantum circuit and produces a complete layout and schedule for this circuit. Quadence can deal with a variety of different Ion trap organizations and error models.

Quadence inserts quantum error correction and performs high-level optimizations on the resulting circuit using an optimization similar to pipeline retiming. It then partitions the datapath, estimates communication, and inserts a custom teleportation network. Finally, it maps and schedules the result. Mapping includes optimized ancilla generation utilizing pipelined ancilla generators. Finally, Quadence performs fault analysis utilizing a modified Monte Carlo technique.

Quadence optimizes circuits utilizing ADCR, a metric modeled after the classic VLSI Area-Delay metric:

ADCR (Area-Delay to Correct Result) = Area x Delay / Prob(Success).

ADCR can be utilized as an optimization metric, leading to interesting tradeoffs between performance, size, and accuracy. For more information, see our publications page.

The Quantum Architecture Research Center is funded by IARPA. More information soon.

The Quantum Architecture research group has a variety of opportunities for people to contribute. This page will list some of them (and will change over time).

We have a variety of opportunities for graduate research in quantum computer architecture.

If you have any interest in research, please contact John Kubiatowicz (kubitron at cs.berkeley.edu) or
Fred Chong (chong at cs.ucsb.edu).

The Quantum Architecture Ressearch group has a variety of opportunities for Berkeley undergraduates.

If you are interested in contributing, contact John Kubiatowicz (kubitron at cs.berkeley.edu)